1. Field of the Invention
The invention relates to a solid electrolyte memory element and a method for fabricating such a memory element which comprises an inert cathode electrode, a reactive anode electrode and a solid electrolyte layer disposed in between the electrodes.
2. Description of the Related Art
The development of semiconductor memory technology is essentially driven by the requirement to increase the performance of the semiconductor memories whilst at the same time reducing the feature sizes. Further miniaturization of the semiconductor memory concepts based on storage capacitors is difficult, however, in particular owing to the large quantity of charge that is required for writing to and reading from the storage capacitors and that leads to a high current demand. Therefore, thought is increasingly being given to new cell concepts that are distinguished by a significantly smaller quantity of charge for the writing and reading operations. Semiconductor memories comprising resistance memory elements provide such promising switching architecture. The resistance memory element is distinguished by two different conductivity states which are in each case assigned a memory state, that is to say “logic 0” or “logic 1”. Generally, to detect the memory state of the resistance memory element, the current flowing via the resistance memory element at an applied read voltage is evaluated.
One possible memory concept with a resistance memory element is the so-called CBRAM (conductive bridging random access memory) cell, in which the resistance memory element comprises an inert cathode electrode, a reactive anode electrode and an ionically conductive carrier material. In this case, the ionically conductive carrier material is generally a solid electrolyte comprising a chalcogenide compound or an oxide. Metal atoms or ions can be incorporated in such a vitreous solid electrolyte in order to obtain an ionic conductor having a high ion mobility at room temperature. Preferably, silver or copper is used as the reactive anode electrode for the resistive element, and tungsten, titanium nitride or doped polysilicon is used for the inert cathode electrode.
The function of the CBRAM cell utilizes the effect whereby metallic ions can be diffused (or infused) into the ionically conductive solid electrolyte material or can be removed from the solid electrolyte material in a controlled manner by application of bipolar voltage pulses. The CBRAM cell can thus switch back and forth between a high-resistance state and a low-resistance state, the different resistance values in each case being assigned a logic state. In this case, the metallic ions introduced into the solid electrolyte layer in a variable manner generally originate from the reactive anode electrode. During the writing operation, that is to say when the metallic ions are diffused into the solid electrolyte material, upon application of a positive write voltage, anode material is oxidized and is dissolved in the solid electrolyte. In this case, the ion diffusion can be controlled by the duration, the intensity and the polarity of the impressed electrical voltage. As soon as a sufficient number of metallic ions have diffused into the solid electrolyte material, a low-resistance metallic or semiconducting bridge forms between the anode electrode and the cathode electrode, as a result of which the electrical resistance of the CBRAM cell decreases greatly.
During the erasure operation, by applying a negative erase voltage, the metallic ions that have diffused into the solid electrolyte material are attracted by the anode electrode, where the metallic ions then deposit again after reduction. This interrupts the low-resistance metallic or semiconducting bridge between the anode electrode and the cathode electrode, which has the effect that the resistance of the CBRAM cell increases greatly. By means of the writing and erasure operations, the CBRAM cell can thus be switched back and forth between the low-resistance state and the high-resistance state which in each case represent a respective logic state. During the read-out of the CBRAM cell, generally the procedure is such that a capacitance is charged or discharged via the CBRAM cell and the electrical potential of the capacitance is then assessed after a predetermined point in time in order thus to determine the logic state of the CBRAM cell.
An objective in memory cell development is high switching speeds for the writing and erasure operations. Thus, in conventional DRAM (dynamic random access memory) and SRAM (static random access memory) cells fabricated using silicon CMOS technology, switching speeds of less than 25 ns are achieved during programming. In the case of CBRAM cells, by contrast, if a method suitable for mass production is used for fabricating the solid electrolyte layer, only significantly lower switching speeds are achieved. This is because the layer producing methods that are usually used in silicon technology, such as, in particular, sputtering methods, chemical vapor deposition (CVD) methods or atomic layer deposition (ALD) methods, produce highly dense layer structures which prevent a rapid ion migration under the influence of an external electric field. Thus, during the application of layers by sputtering, typically layers are produced which, although they are at least partly amorphous, nonetheless have a high-density matrix. In the case of CBRAM cells, when a sputtering process is used for forming the solid electrolyte layer, only switching speeds of approximately 100 ns can be achieved during the writing operation and only switching speeds of 100 μs during the erasure operation. This also holds true when a CVD method or ALD method is used instead of a sputtering method. On account of the high temperatures used in these methods, e.g., 200° C. to 800° C. in the CVD method and 200° C. to 500° C. in the ALD method, nanocrystalline high-density layers form which have only low ion mobility and thus essentially prevent a rapid diffusion of metallic ions during the programming operation and erasure operation of CBRAM cells.
In order to enable faster switching, therefore, methods for fabricating porous solid electrolyte layers have been proposed. Thus, M. N. Kozicki et al. “Can Solid State Electrochemistry Eliminate the Memory Scaling Quandary?” in: IEEE Si Nanoelectronics Workshop, 2002 describes one possibility for fabricating CBRAM cells having switching speeds of approximately 25 ns with thermally vapor-deposited chalcogenide layers as solid electrolyte and additionally vapor-deposited ion donor material. The method of thermal vapor deposition of the solid electrolyte layers that is used by Kozicki et al. is not suitable for mass production, however, since it enables only poor reproducibility and low layer homogeneity in the case of large semiconductor substrates, e.g., 200 mm or 300 mm silicon wafers.
Although the switching speed in CBRAM cells can also be increased by increasing the pulse amplitudes during the writing and erasure operations, the applied electric field strength must not lead to high current densities in the cell that are harmful for the CBRAM cell. The repeated application of high electric fields furthermore intensifies the degradation of the solid electrolyte material.
Furthermore, in the case of low ion mobility, in particular during the erasure operation, the electric fields have to be applied with a long pulse duration in order to achieve a complete resolution of the electrical connection formed by means of the metallic ions between anode electrode and cathode electrode by the metallic ions being transported back to the anode electrode. However, long erase pulses lead to asymmetrical operation of the CBRAM cell or necessitate operating a memory cell array comprising CBRAM cells massively in parallel in order to realize a sufficiently high data rate during erasure.
Therefore, there is a need to provide an improved method for fabricating a solid electrolyte memory element and an improved solid electrolyte memory element which enable high switching speeds under mass production conditions.